1. Field of the Invention
The present invention relates to stacked capacitor structures of semiconductor devices. In particular, the present invention relates to semiconductor device structures which include aluminum plugs disposed between the active device regions and bit lines thereof. More specifically, the present invention relates to semiconductor device structures which include an aluminum-filled trench that electrically connects a bit line to an active device region positioned between adjacent stacked capacitor structures.
2. Background of Related Art
Stacked capacitors are employed in many state of the art semiconductor devices to maintain high storage capacitance despite the ever-increasing densities of such semiconductor devices. Stacked capacitors typically make an electrical connection with a diffusion region, or active device region, of a semiconductor substrate, such as silicon, polysilicon, gallium arsenide, or indium phosphide. Some conventional processes for fabricating stacked capacitors on semiconductor device structures facilitate increased densities by employing electrically conductive layers (e.g., polysilicon layers) that are somewhat convoluted or have large surface areas, and which project outwardly relative to and electrically contact their associated active device regions. The remainders of the capacitor structures are then fabricated on the electrically conductive layers.
Many stacked capacitor structures include electrically conductive contacts between the active device regions and the bit lines thereof. Typically, such electrically conductive contacts are fabricated from polysilicon, which withstands the high temperature processes (e.g., thermal oxidation processes or thermal anneal processes) that are usually performed subsequent to the fabrication of contacts on semiconductor device structures. Such contacts, however, may create a somewhat undesirable amount of contact resistance during operation of the semiconductor device.
Metals have also been employed as the contact material between the active device region and bit lines of semiconductor devices and through the stacked capacitor structures thereof. Again, due to the high process temperatures that are employed following the fabrication of the contacts, metals that will withstand high process temperatures are typically employed in the contacts. Metals that will withstand such high process temperatures are commonly referred to as xe2x80x9crefractory metalsxe2x80x9d and include titanium (Ti), tungsten (W), molybdenum (Mo), and tantalum (Ta). While these metals and their silicides have low resistivities relative to other metals, their resistivities (xcfx81Ti=43-47 xcexcxcexa9-cm, xcfx81w=5.3 xcexcxcexa9-cm, xcfx81Mo=5 xcexcxcexa9-cm, and xcfx81Ta=13-16 xcexcxcexa9-cm) may be somewhat undesirable during the operation of state of the art very large scale integration (VLSI) and ultra large scale integration (ULSI) semiconductor devices. As metals of higher resistivity are employed in such semiconductor devices, the power requirements and operating temperature of such semiconductor devices increase undesirably.
Conventionally, aluminum (Al) has been widely employed as an electrically conductive material in semiconductor devices, as it has low resistivity (xcfx81Al=2.7 xcexcxcexa9-cm) and is compatible with both silicon (Si) and silicon dioxide (SiO2). Aluminum is not, however, typically employed in self-aligned processes due to its inability to withstand high temperature processing, such as the rapid thermal anneal processes that may be employed in fabricating self-aligned silicide layers.
What is needed is a process for fabricating a stacked capacitor structure on a semiconductor device structure which increases the speed of the semiconductor device and reduces the interconnect resistance and power consumption thereof and a stacked capacitor structure and semiconductor device structure fabricated by such a process.
The present invention includes a stacked capacitor structure and methods of fabricating the stacked capacitor structure which address the foregoing needs.
The stacked capacitor structure of the present invention includes a trench disposed over an active device region of a semiconductor device structure. The trench extends downward through the stacked capacitor structure to the active device region of the semiconductor substrate (e.g., silicon, gallium arsenide, indium phosphide), exposing same through the stacked capacitor structure. A layer of self-aligned metal silicide, or xe2x80x9csalicide,xe2x80x9d is disposed within the trench, adjacent the active device region and preferably defining a buried metal diffusion (BMD) layer with the active device region. An aluminum interconnect, or xe2x80x9ccontact,xe2x80x9d is disposed within the trench in contact with the metal silicide and substantially filling the trench. The aluminum interconnect preferably provides an electrical link between the active device region and a bit line that extends above the stacked capacitor structure and electrically contacts the interconnect.
A method of fabricating a stacked capacitor structure is also within the scope of the present invention. The method includes fabricating a stacked capacitor structure over a semiconductor device structure and defining a trench through the stacked capacitor structure and over an active device region of the semiconductor device structure. Processes for fabricating stacked capacitor structures and defining trenches therethrough to an underlying active device region, which may be employed in the method of the present invention, are disclosed in U.S. Pat. No. 5,498,562 (xe2x80x9cthe ""562 patentxe2x80x9d), which issued to Dennison et al. on Mar. 12, 1996, the disclosure of which is hereby incorporated by reference in its entirety.
A layer of a metal that will form a salicide with the silicon exposed through the trench, such as titanium or tungsten, is then deposited over the semiconductor device structure. Known processes, such as rapid thermal anneal (RTA) or silicide deposition processes, may then be employed to form the salicide layer, such as titanium silicide (TiSix, predominantly TiSi2) or tungsten silicide (WSix, predominantly WSi2), which is typically referred to as a xe2x80x9cselectivexe2x80x9d contact, over the active device region of the semiconductor device structure. The formation of suicides such as TiSi2 and WSi2 is said to be self-aligned since the silicide forms only over exposed semiconductor substrate (e.g., silicon and polysilicon) regions of a semiconductor device structure. Everywhere else, the metal film overlies an insulative, substantially non-reactive oxide layer, and may subsequently be removed. Preferably, the metal silicide diffuses into the silicon and defines a BMD layer. A metal nitride layer may also be fabricated over the selective contact by known techniques. Such metal nitride layers are typically referred to as xe2x80x9cbarrierxe2x80x9d layers, as they prevent the diffusion of silicon and silicide into any metal layer or structure that is subsequently fabricated adjacent thereto.
An interconnect is fabricated in the trench by depositing aluminum over the semiconductor device structure in a manner that substantially fills the trench. Known processes, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD) techniques, may be employed to deposit aluminum over the semiconductor device structure. The aluminum that covers other areas of the semiconductor device structure may then be removed by known processes, such as by known planarization (e.g., by chemical-mechanical polishing (CMP) techniques) or etching techniques, which do not remove aluminum from the trench. Additional layers and structures may then be fabricated or defined above the stacked capacitor, including, without limitation, bit lines that are in electrical contact with one or more corresponding aluminum interconnects.
Alternatively, portions of the aluminum layer that overlie the semiconductor device structure may be selectively removed therefrom by known techniques, such as masking and etching processes, in order to define bit lines that are integral with the aluminum interconnects and extend over an active surface of the semiconductor device structure. Such aluminum bit lines may be desirable since they may further reduce contact resistance and are compatible with the adjacent silicon dioxide of the semiconductor device structure.